With the trend of increasingly higher integration of semiconductor devices and finer patterns, a need exists for high resolution, high throughput testing apparatuses. A resolution of 100 nm or less is required for examining defects on a wafer substrate of 100 nm design rule. Also, as the amount of testing is increased to cause an increase in manufacturing steps resulting from higher integration of devices, a higher throughput is required. Further, as devices are formed of an increased number of layers, testing apparatuses are required to have the ability to detect defective contacts (electric defect) of vias which connect wires between layers. While optical defect testing apparatuses are mainly used at present, it is anticipated that electron beam-type defect testing apparatuses will substitute for optical defect testing apparatus as a dominant testing apparatus in the future from a viewpoint of the resolution and defective contact testing capabilities. However, the electron beam-type defect testing apparatus also has a disadvantage in that it is inferior to the optical one in the throughput.
For this reason, a need exists for the development of a high resolution, high throughput testing apparatus which is capable of detecting electric defects. It is said that the resolution of an optical defect testing apparatus is limited to one half of the wavelength of used light, and the limit is approximately 0.2 μm in an example of practically used optical defect detecting apparatus which uses visible light. On the other hand, in electron beam-type systems, scanning electron microscopes (SEM) have been commercially available. The scanning electron microscope has a resolution of 0.1 μm and takes a testing time of eight hours per 20 cm wafer. The electron beam-type system also has a significant feature that it is capable of testing electric defects (broken wires, defective conduction, defective conduction of vias, and so on). However, it takes so long testing time that it is expected to develop a defect testing apparatus which can rapidly conduct a test.
Generally, a testing apparatus is expensive and low in throughput as compared with other process apparatuses, so that it is presently used after critical steps, such as after etching, deposition, CMP (chemical-mechanical polishing) planarization processing, and so on. Now, describing a testing apparatus in accordance with an electron beam-type scanning (SEM) scheme, an SEM based testing apparatus narrows down an electron beam which is linearly irradiated to a sample for scanning. The diameter of the electron beam corresponds to the resolution. On the other hand, by moving a stage in a direction perpendicular to a direction in which the electron beam is scanned, a region under observation is tow-dimensionally irradiated with the electron beam. The width over which the electron beam is scanned generally extends over several hundred μm. A secondary electron beam generated from the sample by the irradiation of the narrowed electron beam (called the “primary electron beam”) is detected by a combination of a scintillator and a photomultiplier (photomultiplier tube) or a semiconductor based detector (using PIN diodes). The coordinates of irradiated positions and the amount of the secondary electron beam (signal strength) are combined to generate an image which is stored in a storage device or output on a CRT (Braun tube).
The foregoing is the principle of SEM (scanning electron microscope). From an image generated by this system, defects on a semiconductor (generally, Si) wafer is detected in the middle of a step. A scanning speed, corresponding to the throughput, is determined by the amount of primary electron beam (current value), diameter of the beam, and a response speed of a detector. Currently available maximum values are 0.1 μm for the beam diameter (which may be regarded as the same as the resolution), 100 nA for the current value, and 100 MHz for the response speed of the detector, in which case it is said that a testing speed is approximately eight hours per wafer of 20 cm diameter.
In the SEM based testing apparatus described above, the cited testing speed is considered substantially as a limit. Therefore, a new scheme is required for increasing the testing speed, i.e., the throughput.